SH7615 Datasheet, PDF (313/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Bit 3—Refresh Control (RFSH): This bit determines whether or not the refresh operation of
DRAM/synchronous DRAM is performed.
Bit 3: RFSH
0
1
Description
No refresh
Refresh
(Initial value)
Bit 2—Refresh Mode (RMODE): When the RFSH bit is 1, this bit selects normal refresh or self-
refresh. When the RFSH bit is 0, do not set this bit to 1. When the RFSH bit is 1, self-refresh
mode is entered immediately after the RMODE bit is set to 1. When the RFSH bit is 1 and this bit
is 0, a CAS-before-RAS refresh or auto-refresh is performed at the interval set in the 8-bit interval
timer. When a refresh request occurs during an external area access, the refresh is performed after
the access cycle is completed. When set for self-refresh, self-refresh mode is entered immediately
unless the chip is in the middle of a synchronous DRAM area access, in which case self-refresh
mode is entered when the access ends. Refresh requests from the interval timer are ignored during
self-refresh.
Bit 2: RMODE
0
1
Description
Normal refresh
Self-refresh
(Initial value)
Rev. 2.00, 03/05, page 275 of 884