SH7615 Datasheet, PDF (576/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

12.4.2 Output Timing for Output Compare
When a compare match occurs, the output level set in the OLVL bit in TOCR is output from the
output compare output pins (FTOA, FTOB). Figure 12.6 shows the timing for output of output
compare A.
Pφ
FRC
N
N+1
N
N+1
OCRA
N
N
Compare
match A
signal
OLVLA
Output
compare A
output pin
FTOA
Clear*
Note: * ↓ Indicates instruction execution by software
Figure 12.6 Output Timing for Output Compare A
12.4.3 FRC Clear Timing
FRC can be cleared on compare match A. Figure 12.7 shows the timing.
Pφ
Compare
match A
signal
FRC
N
H'0000
Figure 12.7 Compare Match A Clear Timing
Rev. 2.00, 03/05, page 538 of 884