SH7615 Datasheet, PDF (312/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

• For synchronous DRAM interface
Bit 7: AMX2 Bit 5: AMX1 Bit 4: AMX0 Description
0
0
0
1
1
0
16-Mbit DRAM (1M × 16 bits), 64-Mbit SDRAM
(2M × 32 bits)^*2
(Initial value)
16-Mbit SDRAM (2M × 8 bits)^*1
16-Mbit SDRAM (4M × 4 bits)^*1
1
4-Mbit SDRAM (256k × 16 bits)
1
0
0
1
64-Mbit SDRAM (4M × 16 bits), 128-Mbit
SDRAM (4M × 32 bits)^*3
64-Mbit SDRAM (8M × 8 bits)^*1, 128-Mbit
SDRAM (8M × 16 bits)^*1*4, 256-Mbit SDRAM
(8M × 32 bits)^*1*5
1
0
Reserved (do not set)
1
2-Mbit SDRAM (128k × 16 bits)
Notes: 1. When SZ bit in MCR is 0 (16-bit bus width), these settings are reserved and must not
be made.
2. See figure 7.34, 64-Mbit Synchronous DRAM (2 Mwords × 32 Bits) Connection
Example, for the method of connection to a 64-Mbit SDRAM (2M × 32 bits).
3. See figure 7.35 for the method of connection to a 128-Mbit SDRAM (4M × 32 bits).
4. Connect a 128-Mbit SDRAM with (8M × 16 bits) through a 32-bit bus as shown in figure
7.36.
5. See figure 7.37 for the method of connection to a 256-Mbit SDRAM (8M × 32 bits).
Bit 6—Memory Data Size (SZ): For synchronous DRAM and DRAM space, the data bus width of
BCR2 is ignored in favor of the specification of this bit.
Bit 6: SZ
0
1
Description
Word (16 bits)
Longword (32 bits)
(Initial value)
Rev. 2.00, 03/05, page 274 of 884