SH7615 Datasheet, PDF (761/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Contention between TGR Write and Compare Match: If a compare match occurs in the T₂
state of a TGR write cycle, the TGR write takes precedence and the compare match signal is
inhibited. A compare match does not occur even if the same value as before is written.
Figure 16.47 shows the timing in this case.
Pφ
Address
TGR write cycle
T₁
T₂
TGR address
Write signal
Compare
match signal
TCNT
Inhibited
N
N+1
TGR
N
M
TGR write data
Figure 16.47 Contention between TGR Write and Compare Match
Rev. 2.00, 03/05, page 723 of 884