SH7615 Datasheet, PDF (315/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Bits 5 to 3—Clock Select Bits (CKS2 to CKS0)
Bit 5: CKS2
0
1
Bit 4: CKS1
0
1
0
1
Bit 3: CKS0
0
1
0
1
0
1
0
1
Description
Count-up disabled
Pφ/4
Pφ/16
Pφ/64
Pφ/256
Pφ/1024
Pφ/2048
Pφ/4096
(Initial value)
Bits 2 to 0—Refresh Count (RRC2 to RRC0): These bits specify the number of consecutive
refreshes to be performed when the refresh timer counter (RTCNT) and refresh time constant
register (RTCOR) values match and a refresh request is issued.
Bit 2: RRC2
0
1
Bit 1: RRC1
0
1
0
1
Bit 0: RRC0
0
1
0
1
0
1
0
1
Description
1 refresh
2 refreshes
4 refreshes
6 refreshes
8 refreshes
Reserved (do not set)
Reserved (do not set)
Reserved (do not set)
(Initial value)
7.2.9 Refresh Timer Counter (RTCNT)
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 2.00, 03/05, page 277 of 884