SH7615 Datasheet, PDF (653/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

1
Serial
data
Start
bit
0 D0
Data
Multi-
proces- Stop Start
sor bit bit bit
D1
D7 0/1 1 0 D0 D1
Multi-
proces- Stop
sor bit bit
D7 0/1 1
1
Idle state
(mark state)
TDFE
TEND
TXI interrupt
request
Data written to SCFTDR
and TDFE flag cleared
to 0 by TXI interrupt handler
TXI interrupt
request
One frame
Figure 14.13 Example of SCIF Transmit Operation
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit, LSB-First Transfer)
• Multiprocessor Serial Data Reception
Figure 14.14 shows a sample flowchart for multiprocessor serial reception.
Use the following procedure for multiprocessor serial data reception after enabling the SCIF
for reception.
Rev. 2.00, 03/05, page 615 of 884