SH7615 Datasheet, PDF (276/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

3. The INTC determines the priority of the user break interrupt. As the priority level of a user
break interrupt is 15, the interrupt is accepted if the level set in the interrupt mask bits (I3 to I0)
in the status register (SR) is 14 or less. If the level set in bits I3 to I0 is 15, the user break
interrupt is not accepted, but is held pending until it can be. For details of priority
determination, see section 5, Interrupt Controller (INTC).
4. If the user break interrupt is accepted after its priority is determined, the CPU begins user
break interrupt exception handling.
5. Whether a set condition is matched or not can be ascertained from the respective condition
match flag (CMFCA, CMFPA, CMFCB, CMFPB, CMFCC, CMFPC, CMFCD, or CMFPD).
These flags are set by a match with the set condition, but are not reset. Therefore, if the setting
of a particular flag is to be checked again, the flag must be cleared by writing 0.
When an execution-times break is specified for channel C or D, the CMFCC, CMFPC,
CMFCD, or CMFPD flag is set when the number of executions matches the number of
executions specified by BETRC or BETRD.
6.3.2 Instruction Fetch Cycle Break
1. If a CPU/instruction fetch/read/word setting is made in the break bus cycle register (BBRA,
BBRB, BBRC, or BBRD), a CPU instruction fetch cycle can be selected as a break condition.
In this case, it is possible to specify whether the break is to be effected before or after
execution of the relevant instruction by means of the PCBA/PCBB/PCBC/PCBD bit in the
break control register (BRCR).
2. In the case of an instruction for which pre-execution is set as the break condition, the break is
performed when it has been confirmed that the instruction has been fetched and is to be
executed. Consequently, a break cannot be set for an overrun-fetched instruction (an
instruction fetched but not executed in the event of a branch or interrupt transition). If a break
is set for the delay slot of a delayed branch instruction, or for the instruction following an
instruction for which interrupts are prohibited, such as LCD, an interrupt is generated before
execution of the next instruction at which interrupts are accepted.
3. With the post-execution condition, an interrupt is generated after execution of the instruction
set as the break condition, and before execution of the following instruction. As in 2 above, a
break cannot be set for an overrun-fetched instruction. If a break is set for a delayed branch
instruction, or for an instruction for which interrupts are prohibited, such as LCD, an interrupt
is generated before execution of the next instruction at which interrupts are accepted.
4. When an instruction fetch cycle is set for channel C or D, break data register C (BDRC) or
break data register D (BDRD) is ignored. Therefore, break data need not be set for an
instruction fetch cycle break.
Rev. 2.00, 03/05, page 238 of 884