SH7615 Datasheet, PDF (228/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Bits 3 to 0:
IRQ3F to IRQ0F
0
Detection Setting
Level detection
Edge detection
1
Level detection
Edge detection
Note: n = 0 to 3
Description
There is no IRQn interrupt request
(Initial value)
[Clearing condition]
When IRLn input is high
An IRQn interrupt request has not been detected
(Initial value)
[Clearing conditions]
• When 0 is written to IRQnF after reading IRQnF = 1
• When an IRQn interrupt is accepted
There is an IRQn interrupt request
[Setting condition]
When IRLn input is low
An IRQn interrupt request has been detected
[Setting condition]
When an IRLn input edge is detected
Rev. 2.00, 03/05, page 190 of 884