SH7615 Datasheet, PDF (679/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

1st
initialization
Initialization
Clear TE and RE bits to 0 in SCSCR
Set TFRST and RFRST bits to 1 in SCFCR
Reset the transmit/receive data resister
Set CKE1 and CKE0 bits in SCSCR
(leaving TE and RE bits cleared to 0)
Set transmit/receive format in SCSMR
Set value in SCBRR
Wait
No
1-bit interval elapsed?
Yes
Set RTRG1, RTRG0 and TTRG1, TTRG0 bits in SCFCR, [1] Trigger setting
and clear TFRST and RFRST bits to 0
Set the transmit/receive FIFO data count
Set TE or RE bit to 1 in SCSCR,
and set RIE, TIE and MPIE bits
2nd
initialization
Clear TE and RE bits to 0 in SCSCR
Set TFRST and RFRST bits to 1 in SCFCR
Set CKE1 and CKE0 bits in SCSCR
(leaving TE and RE bits cleared to 0)
Set transmit/receive format in SCSMR
[2] Trigger setting
RXI request may be set when the value of the
receive FIFO data count has been changed from
1st initialization.
Set value in SCBRR
Wait
No
1-bit interval elapsed?
Yes
Set RTRG1, RTRG0 and TTRG1, TTRG0 bits in SCFCR,
and clear TFRST and RFRST bits to 0
Set TE or RE bit to 1 in SCSCR,
and set RIE, TIE and MPIE bits
Figure 14.27 Example of SCIF Initialization Flowchart
Rev. 2.00, 03/05, page 641 of 884