SH7615 Datasheet, PDF (616/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Bit 7—Receive Error (ER)
Bit 7: ER
Description
0
Reception in progress, or reception has ended normally^*1
(Initial value)
[Clearing conditions]
• In a reset or in standby mode
• When 0 is written to ER after reading ER = 1
1
A framing error, parity error, or overrun error occurred during reception
[Setting conditions]
• When the SCIF checks whether the stop bit at the end of the receive data is
1 when reception ends, and the stop bit is 0*²
• When, in reception, the number of 1-bits in the receive data plus the parity
bit does not match the parity setting (even or odd) specified by the O/E bit
in the serial mode register (SCSMR)
• When the next serial receive operation is completed while there are 16
receive data bytes in SCFRDR
Notes: 1. The ER flag is not affected and retains its previous state when the RE bit in SCSCR is
cleared to 0. When a framing error or parity error occurs, the receive data is still
transferred to SCFRDR, and reception is then halted or continued according to the
setting of the EI bit. When an overrun error occurs, the receive data is not transferred to
SCFRDR and reception cannot be continued.
2. In 2-stop-bit mode, only the first stop bit is checked for a value of 1; the second stop bit
is not checked.
Bit 6—Transmit End (TEND): Indicates that there is no valid data in SCFTDR when the last bit of
the transmit character is sent, and transmission has been ended.
Bit 6: TEND
0
1
Description
Transmission is in progress
[Clearing condition]
When data is written to SCFTDR while TE = 1
Transmission has been ended
(Initial value)
[Setting conditions]
• In a reset or in standby mode
• When the TE bit in SCSCR is 0
• When there is no transmit data in SCFTDR on transmission of the last bit of
a 1-byte serial transmit character
Rev. 2.00, 03/05, page 578 of 884