SH7615 Datasheet, PDF (719/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Bit 5—Underflow Flag (TCFU): Status flag that indicates that TCNT underflow has occurred
when channels 1 and 2 are set to phase counting mode.
In channel 0, bit 5 is reserved. It is always read as 0 and cannot be modified.
Bit 5: TCFU
0
1
Description
[Clearing condition]
(Initial value)
When 0 is written to TCFU after reading TCFU = 1
[Setting condition]
When the TCNT value underflows (changes from H'0000 to H'FFFF)
Bit 4—Overflow Flag (TCFV): Status flag that indicates that TCNT overflow has occurred.
Bit 4: TCFV
0
1
Description
[Clearing condition]
(Initial value)
When 0 is written to TCFV after reading TCFV = 1
[Setting condition]
When the TCNT value overflows (changes from H'FFFF to H'0000 )
Bit 3—Input Capture/Output Compare Flag D (TGFD): Status flag that indicates the occurrence of
TGRD input capture or compare match in channel 0.
In channels 1 and 2, bit 3 is reserved. It is always read as 0 and cannot be modified.
Bit 3: TGFD
0
1
Description
[Clearing conditions]
(Initial value)
• When DMAC is activated by TGID interrupt while DRCR setting in DMAC is
TGI0D
• When 0 is written to TGFD after reading TGFD = 1
[Setting conditions]
• When TCNT = TGRD while TGRD is functioning as output compare
register
• When TCNT value is transferred to TGRD by input capture signal while
TGRD is functioning as input capture register
Rev. 2.00, 03/05, page 681 of 884