SH7615 Datasheet, PDF (532/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

• Burst Mode
In burst mode, once the DMAC gets the bus, the transfer continues until the transfer end
condition is satisfied. When external request mode is used with level detection of the DREQ
pin, however, negating DREQ will pass the bus to the other bus master after completion of the
bus cycle of the DMAC that currently has an acknowledged request, even if the transfer end
conditions have not been satisfied. When the transfer request source is an on-chip peripheral
module, however, cycle-steal mode is always used.
Figure 11.11 shows an example of DMA transfer timing in burst mode. The transfer conditions
for the example in the figure are as shown below.
• Single address mode
• DREQn level detection
DREQn
Bus
cycle ^{CPU CPU CPU DMAC DMAC DMAC DMAC CPU CPU CPU}
Figure 11.11 DMA Transfer Timing in Burst Mode
(Single Address, DREQn Falling-Edge Detection)
Refreshes cannot be performed during a burst transfer, so ensure that the number of transfers
satisfies the refresh request period when a memory requiring refreshing is used. When the
transfer request source is an external request (DREQn) in burst mode, set the DS bit of CHCR0
and CHCR1 to 1 (edge detection). If the DS bits of CHCR0 and CHCR1 are set to 0 (level
detection), operation is not guaranteed.
Rev. 2.00, 03/05, page 494 of 884