SH7615 Datasheet, PDF (560/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

DACKn (n = 0 or 1) assert timing and count:
Bus Width
16-bit bus width
8-bit bus width
16-Byte Unit
Error timing 1 x 4
Error timing 2 x 4
Longword Unit
Error timing 1 x 1
Error timing 2 x 1
Word Unit
—
Error timing 1 x 1
Conditions:
When the following conditions are all satisfied, DACKn (n = 0 or 1) is output with a wrong
timing.
(1) Iφ:Eφ = 1:1
(2) DMA transfer to an ordinary space or burst ROM space
(3) 16-byte or longword DMA transfer to a 16-bit width space or 16-byte, longword, or word
DMA transfer to an 8-bit width space, which generates multiple bus cycles
Countermeasures:
This problem is avoided by any of the following countermeasures.
(1) Specify a clock ratio except t_Ecyc:t_Pcyc 1:1.
(2) Use 32-bit bus width.
(3) When the bus width is 16 bits, perform word or byte DMA transfer.
(4) When the bus width is 8 bits, perform byte DMA transfer.
13. DMAC does not perform DMA transfer on channel 1 by an on-chip peripheral module request
Phenomenon:
(1) DMAC does not perform DMA transfer on channel 1 by an on-chip peripheral module
request.
When channel 0 of the on-chip DMAC is set to cycle-steal mode and channel 1 is set to on-
chip peripheral module request mode, the DMAC may not perform DMA transfer on
channel 1.
Conditions:
(1) Conditions for malfunction in DMA transfer on channel 1 by an on-chip peripheral module
request
When the following conditions are all satisfied, the DMAC does not perform DMA transfer
on channel 1 by an on-chip peripheral module request.
(a) DMAC channels 0 and 1 are both enabled.
(b) DMAC channel 0 is set to cycle-steal mode.
(c) DMAC channel 1 is set to cycle-steal mode, dual address mode, and on-chip peripheral
module request mode.
(d) Round-robin mode is specified as the DMAC priority mode.
Rev. 2.00, 03/05, page 522 of 884