SH7615 Datasheet, PDF (615/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

14.2.7 Serial Status 1 Register (SC1SSR)
Bit:
Initial value:
R/W:
15
PER3
0
R
14
PER2
0
R
13
PER1
0
R
12
PER0
0
R
11
FER3
0
R
10
FER2
0
R
9
FER1
0
R
8
FER0
0
R
Bit:
Initial value:
R/W:
7
ER
0
R/(W)^*
6
TEND
1
R
5
TDFE
1
R/(W)^*
4
BRK
0
R/(W)^*
Note: * Only 0 can be written, to clear the flag.
3
FER
0
R
2
PER
0
R
1
RDF
0
R/(W)^*
0
DR
0
R/(W)^*
The serial status 1 register (SC1SSR) is a 16-bit register in which the lower 8 bits consist of status
flags that indicate the operating status of the SCIF, and the upper 8 bits indicate the number of
receive errors in the data in the receive FIFO register.
SC1SSR can be read or written to at all times. However, 1 cannot be written to the ER, TDFE,
BRK, RDF, and DR status flags. Also note that in order to clear these flags to 0, they must first be
read as 1. The TEND, FER, and PER flags are read-only and cannot be modified.
SC1SSR is initialized to H'0084 by a reset, by the module standby function, and in standby mode.
Bits 15 to 12—Parity Error Count 3 to 0 (PER3 to PER0): These bits indicate the number of data
bytes in which a parity error occurred in the receive data in the receive FIFO data register.
These bits are cleared by reading all the receive data in the receive FIFO data register, or by
setting the RFRST bit to 1 in SCFCR and resetting the receive FIFO data register to the empty
state.
Bits 11 to 8—Framing Error Count 3 to 0 (FER3 to FER0): These bits indicate the number of data
bytes in which a framing error occurred in the receive data in the receive FIFO data register.
These bits are cleared by reading all the receive data in the receive FIFO data register, or by
setting the RFRST bit to 1 in SCFCR and resetting the receive FIFO data register to the empty
state.
Rev. 2.00, 03/05, page 577 of 884