SH7615 Datasheet, PDF (620/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

14.2.8 Serial Status 2 Register (SC2SSR)
Bit: 7
6
5
4
TLM RLM
N1
N0
Initial value: 0
0
1
0
R/W: R/W R/W R/W R/W
Note: * Only 0 can be written, to clear the flag.
3
MPB
0
R
2
MPBT
0
R/W
1
EI
0
R/W
0
ORER
0
R/(W)^*
The serial status 2 register (SC2SSR) is an 8-bit register.
SC2SSR can be read or written to at all times. However, 1 cannot be written to the ORER flag.
Also note that in order to clear this flag to 0, they must first be read as 1.
SC2SSR is initialized to H'20 by a reset, by the module standby function, and in standby mode.
Bit 7—Transmit LSB/MSB-First Select (TLM): Selects LSB-first or MSB-first mode in data
transmission.
Bit 7: TLM
0
1
Description
LSB-first transmission
MSB-first transmission
(Initial value)
Bit 6—Receive LSB/MSB-First Select (RLM): Selects LSB-first or MSB-first mode in data
reception.
Bit 6: RLM
0
1
Description
LSB-first reception
MSB-first reception
(Initial value)
Bits 5 and 4—Clock Bit Rate Ratio (N1, N0): These bits select the ratio of the base clock to the bit
rate.
Bit 5:
N1
0
1
Bit 4:
N0
0
1
0
1
Description
SCIF operates on base clock of 4 times the bit rate
SCIF operates on base clock of 8 times the bit rate
SCIF operates on base clock of 16 times the bit rate
Setting prohibited
(Initial value)
Rev. 2.00, 03/05, page 582 of 884