SH7615 Datasheet, PDF (320/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

7.4 Accessing Ordinary Space
7.4.1 Basic Timing
A strobe signal is output by ordinary space accesses of CS0 to CS4 spaces to provide primarily for
SRAM direct connections. Figure 7.8 shows the basic timing of ordinary space accesses. Ordinary
accesses without waits end in 2 cycles. The BS signal is asserted for 1 cycle to indicate the start of
the bus cycle. The CSn signal is negated by the fall of clock T2 to ensure the negate period. The
negate period is thus half a cycle when accessed at the minimum pitch.
The access size is not specified during a read. The correct access start address will be output to the
LSB of the address, but since no access size is specified, the read will always be 32 bits for 32-bit
devices and 16 bits for 16-bit devices. For writes, only the WE signal of the byte that will be
written is asserted. For 32-bit devices, WE3 specifies writing to a 4n address and WE0 specifies
writing to a 4n+3 address. For 16-bit devices, WE1 specifies writing to a 2n address and WE0
specifies writing to a 2n+1 address. For 8-bit devices, only WE0 is used.
When data buses are provided with buffers, the RD signal must be used for data output in the read
direction. When RD/WR signals do not perform accesses, the chip stays in read status, so there is a
danger of conflicts occurring with output when this is used to control the external data buffer.
Rev. 2.00, 03/05, page 282 of 884