SH7615 Datasheet, PDF (548/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Clock
Bus cycle
DREQn
(Rising-edge
detection)
DACKn
(Active high)
CPU
1st
acceptance
CPU
DMAC
2nd
acceptance
DMAC
CPU
CPU
DMAC
3rd
acceptance
DMAC
Figure 11.33 DREQn/DACKn Handshaking
• Edge Detection—1/2/4-Byte Transfer
Transfer Width
Transfer bus mode
Byte/Word/Longword
Cycle-steal mode
DREQn Detection
Method
DACKn output timing
Transfer address mode Dual/single mode
Bus cycle
Edge Detection
Read DACK/write
DACK
Basic bus cycle
Clock
Bus cycle
CPU
CPU
DMAC CPU
DREQn
(Active high)
DACKn
(Active high)
1st
acceptance
Blind zone
2nd
acceptance
Requests acceptable
Figure 11.34 DREQn Pin Input Detection Timing in Cycle-Steal Mode with Edge Detection
Rev. 2.00, 03/05, page 510 of 884