 English |
|
|
|
|
|
|
|
| SH7615 Datasheet, PDF (852/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7600 Series | |||
| |||
| ◁ |
CKIO
Address
upper bits
Address
lower bits
BS
CSn
RD/WR
TC
TW
Td1
Td2
Td3
Td4
Tde
RD
WEn â
DQMxx
D31âD0
tDQMD
DACKn
WAIT
RAS
CAS â
OE
CKE
Note: DACKn waveform when active-high is specified
Figure 21.20 Synchronous DRAM Read Bus Cycle
(Bank Active, Same Row Access, CAS Latency = 2 Cycles)
Rev. 2.00, 03/05, page 814 of 884
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese