SH7615 Datasheet, PDF (392/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

The DMAC can access on-chip memory other than cache memory, but cannot access cache
memory. When the DMAC causes a write to external memory, the external memory contents and
the cache contents may be different. When external memory contents are rewritten by a DMA
transfer, the cache memory must be purged by software if there is a possibility that the data for
that address is present in the cache.
When the CPU starts a read access, if the access is to a cache area, a cache search is first
performed. This takes one cycle. If there is data in the cache, it fetches it and completes the access.
If there is no data in the cache, a cache filling is performed via the internal bus, so four
consecutive longword reads occur. For misses that occur when byte or word operands are accessed
or branches occur to odd word boundaries (4n + 2 addresses), the filling is always performed by
longword accesses on the chip-external interface. In the cache-through area, the access is to the
actual access address. When the access is an instruction fetch, the access size is always longword.
For cache-through areas and on-chip peripheral module read cycles, after an extra cycle is added
to determine the cycle, the read cycle is started through the internal bus. Read data is sent to the
CPU through the cache bus.
When write cycles access the cache area, the cache is searched. When the data of the relevant
address is found, it is written here. The actual write occurs in parallel to this via the internal bus in
write-through mode. In write-back mode, the actual write is not performed until a replace
operation occurs for the relevant address. When the right to use the internal bus is held, the CPU is
notified that the write is completed without waiting for the end of the actual off-chip write. When
the right to use the internal bus is not held, as when it is being used by the DMAC or the like, there
is a wait until the bus is acquired before the CPU is notified of completion.
Accesses to cache-through areas and on-chip peripheral modules work the same as in the cache
area, except for the cache search and write.
Because the bus state controller has one level of write buffer, the internal bus can be used for
another access even when the chip-external bus cycle has not ended. After a write has been
performed to low-speed memory off the chip, performing a read or write with an on-chip
peripheral module enables an access to the on-chip peripheral module without having to wait for
the completion of the write to low-speed memory.
During reads, the CPU always has to wait for the end of the operation. To immediately continue
processing after checking that the write to the device of actual data has ended, perform a dummy
read access to the same address consecutively to check that the write has ended.
The bus state controller’s write buffer functions in the same way during accesses from the DMAC.
A dual-address DMA transfer thus starts in the next read cycle without waiting for the end of the
write cycle. When both the source address and destination address of the DMA are external spaces
to the chip, however, it must wait until the completion of the previous write cycle before starting
the next read cycle.
Rev. 2.00, 03/05, page 354 of 884