SH7615 Datasheet, PDF (368/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

7.6.4 Wait State Control
When the clock frequency is raised, 1 cycle may not always be sufficient for all states to end, as in
basic access. Setting bits in WCR1, WCR2 and MCR enables the state to be lengthened. Figure
7.41 shows an example of lengthening a state using settings.
The Tp cycle (which ensures a sufficient RAS precharge time) can be extended from 1 cycle to 2
cycles by insertion of a Tpw cycle by means of the TRP1, TRP0 bit in MCR. The number of
cycles between RAS assert and CASn assert can be extended from 1 cycle to 3 cycles by inserting
a Trw cycle by means of the RCD1, RCD0 bit in MCR. The number of cycles from CASn assert
to the end of access can be extended from 1 cycle to 3 cycles by setting the W31/W30 bits in
WCR1. When external wait mask bit A3WM in WCR2 is cleared to 0 and bits W31 and W30 in
WCR1 are set to a value other than 00, the external wait pin is also sampled, so the number of
cycles can be further increased. When bit A3WM in WCR2 is set to 1, external wait input is
ignored regardless of the setting of W31 and W30 in WCR1. Figure 7.42 shows the timing of wait
state control using the WAIT pin.
In either case, when consecutive accesses occur, the Tp cycle access overlaps the Tc2 cycle of the
previous access. In DRAM access, BS is not asserted, and so RAS, CASn, RD, etc., should be
used for WAIT pin control.
Rev. 2.00, 03/05, page 330 of 884