SH7615 Datasheet, PDF (594/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

13.3 Operation
13.3.1 Operation in Watchdog Timer Mode
IT To use the WDT as a watchdog timer, set the WT/ and TME bits in WTCSR to 1. Software
must prevent WTCNT overflow by rewriting the WTCNT value (normally by writing H'00) before
overflow occurs. Thus, WTCNT will not overflow while the system is operating normally, but if
WDTOVF WTCNT fails to be rewritten and overflows occur due to a system crash or the like, a
WDTOVF signal is output (figure 13.4). The
signal can be used to reset the system. The
WDTOVF signal is output for 512 φ clock cycles.
WDTOVF ^{If the RSTE bit in RSTCSR is set to 1, a signal to reset the chip will be generated internally}
simultaneously with the
signal when WTCNT overflows. Either a power-on reset or a
manual reset can be selected by the RSTS bit. The internal reset signal is output for 2048 φ clock
cycles.
RES If a reset due to the input signal from the pin and a reset due to WDT overflow occur
RES simultaneously, the reset takes priority and the WOVF bit in RSTCSR is cleared to 0.
Rev. 2.00, 03/05, page 556 of 884