SH7615 Datasheet, PDF (56/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Type
Bus control
Symbol
CAS
OE
DQMUU/
WE3
DQMUL/
WE2
DQMLU/
WE1
DQMLL/
WE0
CAS3
CAS2
CAS1
CAS0
CKE
REFOUT
RD/WR
BUSHiZ
BH
STATS0,
STATS1
I/O
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Output
Output
Name
Function
Column
Synchronous DRAM CAS signal
address strobe
Output enable EDO DRAM output enable signal
Used in access in RAS down mode
Highest byte
access
SRAM/synchronous DRAM highest byte
select signal
Second byte
access
SRAM/synchronous DRAM second byte
select signal
Third byte
access
SRAM/synchronous DRAM third byte
select signal
Lowest byte
access
SRAM/synchronous DRAM lowest byte
select signal
Column address DRAM highest byte select signal
strobe 3
Column address DRAM second byte select signal
strobe 2
Column address DRAM third byte select signal
strobe 1
Column address DRAM lowest byte select signal
strobe 0
Clock enable Synchronous DRAM clock enable signal
Refresh out
Signal requesting refresh execution
when the bus is released
Read/write
DRAM/synchronous DRAM write signal
Bus high
impedance
Signal used in combination with WAIT
signal to place bus and strobe signals in
the high-impedance (HiZ) state without
ending the bus cycle
Burst hint
Asserted at the start of a DMA burst,
negated one bus cycle before the end of
the burst
Status
CPU, DMAC, and E-DMAC status
information
Rev. 2.00, 03/05, page 18 of 884