HC4GX15 Datasheet, PDF (99/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 7: External Memory Interfaces in HardCopy IV Devices
7–33
HardCopy IV External Memory Interface Features
DQS Logic Block
Each DQS and CQn pin is connected to a separate DQS logic block, which consists of
the DQS delay chains, the update enable circuitry, and the DQS postamble circuitry as
shown in Figure 7–19.
Figure 7–19. HardCopy IV DQS Logic Block
DQS Delay Chain
Bypass
DQS or
CQn Pin
Phase offset
6
settings from
DQS phase shift
circuitry
DQS delay
settings from the
6
DQS phase-
shift circuitry
6
6
6
6
DQ
6
6
DQ
Input Reference
Clock (2)
DQS Enable
B
A
reset
gated_dqs control
DFF
PRN
QD
V_CC
DQS'
CLR
DQS bus
dqsenable (1)
Update
Enable
Circuitry
Postamble
Enable
Resynchronization
Clock
Postamble
Clock
DQ
DQ
DQ
Notes to Figure 7–19:
(1) The dqsenable signal can also come from the HardCopy IV core fabric.
(2) The input reference clock for the DQS phase-shift circuitry can come from a PLL output clock or an input clock pin. Refer to Table 7–9 and
Table 7–13 for the exact PLL and input clock pin.
DQS Delay Chain
The DQS delay chains consist of a set of variable delay elements to allow the input
DQS and CQn signals to be shifted by the amount specified by the DQS phase-shift
circuitry or the core array. There are four delay elements in the DQS delay chain; the
first delay chain closest to the DQS pin can be shifted either by the DQS delay settings
or by the sum of the DQS delay setting and the phase-offset setting. The number of
delay chains required is transparent to you because the ALTMEMPHY megafunction
automatically sets it when you choose the operating frequency. The DQS delay
settings can come from the DQS phase-shift circuitry on either end of the I/O banks or
from the core array.
© January 2010 Altera Corporation
HardCopy IV Device Handbook, Volume 1