HC4GX15 Datasheet, PDF (31/668 Pages) Altera Corporation – HardCopy IV Device Handbook

3. DSP Block Implementation in
HardCopy IV Devices
HIV51003-1.0
Stratix^® IV devices have dedicated high-performance digital signal processing (DSP)
blocks that are distributed throughout the core fabric. These hard-wired DSP blocks
are ideal for applications such as high performance computing (HPC), video
compression/decompression, and voice over internet protocol (VoIP). Such
applications typically require a large number of mathematical computations.
Stratix IV DSP blocks consist of a combination of dedicated elements that perform
multiplication, addition, subtraction, accumulation, summation, and dynamic shift
operations. In HardCopy^® IV devices, these DSP functions are constructed using
HCells instead of dedicated DSP blocks. HCells allow HardCopy IV devices to have
the same functionality as Stratix IV DSP blocks. In addition, DSP blocks implemented
with HCells provide significant static power savings because only the HCells needed
to implement the functions are used.
This chapter contains the following sections:
■ “DSP Function Implementation”
■ “DSP Operational Mode and Feature Support” on page 3–2
DSP Function Implementation
A Stratix IV DSP block consists of an input register bank, multiplier adders, pipeline
register bank, second-stage adders/accumulator, round and saturation units, and
second adder register and output register bank. In the HardCopy IV devices, HCells
make up the device logic fabric. HCells are a collection of logic transistors that are
connected together to provide the same DSP functions as the Stratix IV DSP blocks.
HCells are also used to implement the Stratix IV adaptive logic module (ALM) and
logic array block (LAB) functions in the HardCopy IV devices.
f For more information about ALM, LAB, and memory logic array block (MLAB)
implementation in HardCopy IV devices, refer to the Logic Array Block and Adaptive
Logic Module Implementation in HardCopy IV Devices chapter.
The Quartus^® II software uses a library of pre-characterized HCell macros to place
Stratix IV DSP configurations into the HardCopy IV HCell-based logic fabric. An
HCell macro (HCM) defines how a group of HCells are connected together. Based on
design requirements, the Quartus II software chooses the appropriate DSP HCell
macros to implement the DSP functionality. In HardCopy IV devices, HCell macros
implement Stratix IV DSP block functionality with area efficiency and performance on
par with the dedicated DSP blocks in Stratix IV devices.
Only HCells that are required to implement the design’s DSP functions are enabled.
HCells not needed for DSP functions can be used for ALM configurations, which
results in efficient logic usage. In addition to area management, the placement of these
HCell macros allows for optimized routing and performance.
© December 2008 Altera Corporation
HardCopy IV Device Handbook, Volume 1