HC4GX15 Datasheet, PDF (74/668 Pages) Altera Corporation – HardCopy IV Device Handbook

7–8
Chapter 7: External Memory Interfaces in HardCopy IV Devices
Memory Interfaces Pin Support
The DQS and DQ pin locations are fixed in the pin table. Memory interface circuitry is
available in every HardCopy IV I/O bank. All memory interface pins support the I/O
standards required to support DDR3, DDR2, DDR SDRAM, QDRII+, QDRII SRAM,
and RLDRAM II devices.
HardCopy IV devices support DQS and DQ signals with DQ bus modes of ×4, ×8/×9,
×16/×18, or ×32/×36, although not all devices support DQS bus mode ×32/×36.
When any of these pins are not used for memory interfacing, you can use them as user
I/Os. In addition, you can use any DQSn or CQn pin not used for clocking as DQ
(data) pins. Table 7–4 lists pin support per DQS/DQ bus mode, including the DQS
and DQSn/CQn pin pair.
Table 7–4. HardCopy IV DQS/DQ Bus Mode Pins (Note 1), (2), (3), (4), (5)
Mode
DQSn
CQn
Support Support
Parity or DM
(Optional)
QVLD (Optional)
Typical Number of Maximum Number
Data Pins per
of Data Pins per
Group
Group
×4
Yes
No
No
No
4
5
×8/×9
Yes
Yes
Yes
Yes
8 or 9
11
×16/×18 Yes
Yes
Yes
Yes
16 or 18
23
×32/×36 Yes
Yes
Yes
Yes
32 or 36
47
Notes to Table 7–4:
(1) The QVLD pin is not used in the ALTMEMPHY megafunction.
(2) This represents the maximum number of DQ pins (including parity, data mask, and QVLD pins) connected to the DQS bus network with
single-ended DQS signaling. When you use differential or complementary DQS signaling, the maximum number of data per group decreases
by one. This number may vary per DQS/DQ group in a particular device. Check the pin table for the accurate number per group.
(3) Two ×4 DQS/DQ groups are stitched to make a ×8/×9 group, so there are a total of 12 pins in this group.
(4) Four ×4 DQS/DQ groups are stitched to make a ×16/×18 group.
(5) Eight ×4 DQS/DQ groups are stitched to make a ×32/×36 group.
You can also use DQS/DQSn pins in some of the ×4 groups as R_UP/R_DN pins (listed in
the pin table). You cannot use a ×4 DQS/DQ group for memory interfaces if any of its
pin members are being used as R_UP and R_DN pins for OCT calibration. You may use the
×8/×9 group that includes this ×4 DQS/DQ group, if either of the following
circumstances apply:
■ You are not using DM pins with your differential DQS pins
■ You are not using complementary or differential DQS pins
You can do this because a DQS/DQ ×8/×9 group is comprised of 12 pins, as the
groups are formed by stitching two DQS/DQ groups in ×4 mode with six total pins
each (Table 7–4). A typical ×8 memory interface contains 10 pins, consisting of one
DQS, one DM, and eight DQ pins. If you choose your pin assignment carefully, you
can use the two extra pins for R_UP and R_DN. In a DDR3 SDRAM interface, you must use
differential DQS, which means that you only have one extra pin. In this case, pick
different pin locations for the R_UP and R_DN pins (for example, in the bank that contains
the address and command pins).
HardCopy IV Device Handbook, Volume 1
© January 2010 Altera Corporation