HC4GX15 Datasheet, PDF (207/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 3: Mapping Stratix IV Device Resources to HardCopy IV Devices
3–5
HardCopy IV and Stratix IV Mapping Options
Table 3–3. HardCopy IV GX ASIC Features
HardCopy IV GX
ASIC
Stratix IV GX
FPGA
Prototype
ASIC
Equivalent
Gates (1)
Transceivers
6.5+Gbps (2)
M9K
Blocks
M144K
Blocks
Total
Dedicated
RAM Bits
(not
including
MLABs) (3)
18 x 18-Bit
Multipliers
(FIR Mode) PLLs
EP4SGX70
2.8 M
8, 0
462
16
6,462 Kb
384
3
EP4SGX110
3.8 M
8, 0
660
16
8,244 Kb
512
3
HC4GX15
EP4SGX180
EP4SGX230
6.7 M
9.2 M
8, 0
660
20
8,820 Kb
920
3
8, 0
660
22
9,108 Kb
1288
3
EP4SGX290
7.7 M
8, 0
660
24
9,396 Kb
832
2
EP4SGX360
9.4 M
8, 0
660
24
9,396 Kb
1040
2
EP4SGX110
3.8 M
16, 0
660
16
8,244 Kb
512
4
EP4SGX180
6.7 M
16, 8 (6)
936
20
11,304 Kb
920
6
HC4GX25
EP4SGX230
EP4SGX290
9.2M
7.7 M
16, 8 (6)
16, 8 (6)
936
22
11,592 Kb
1288
6
936
36
13,608 Kb
832
6 (4)
EP4SGX360
9.4 M
16, 8 (6)
936
36
13,608 Kb
1040
6 (4)
EP4SGX530
11.5 M
16, 8
936
36
13,608 Kb
1024
6
EP4SGX180
6.7 M
24, 12 (7)
950
20
11,430 Kb
920
8
EP4SGX230
9.2 M
24, 12 (7)
1235
22
14,283 Kb
1288
8 (5)
HC4GX35
EP4SGX290
7.7 M
24, 12 (7)
936
36
13,608 Kb
832
8
EP4SGX360
9.4 M
24, 12 (7)
1248
48
18,144 Kb
1040
8 (5)
EP4SGX530
11.5 M
24, 12 (7)
1280
64
20,736 Kb
1024
8 (5)
Notes to Table 3–3:
(1) This is the number of ASIC-equivalent gates available in the HardCopy IV GX base array, shared between both adaptive logic module (ALM) logic
and DSP functions from a Stratix IV GX FPGA prototype. The number of usable ASIC equivalent gates is bounded by the number of ALMs in the
companion Stratix IV GX FPGA device.
(2) The first number indicates the number of transceivers and the second number indicates the number of CMU (PMA only) transceivers.
(3) HardCopy IV GX devices do not have dedicated MLABs, but the Stratix IV GX MLAB features and functions are supported in HardCopy IV GX
devices.
(4) This device has six PLLs in the F1152 package and four PLLs in the F780 package.
(5) This device has eight PLLs in the F1517 package and six PLLs in the F1152 package.
(6) Devices in the cost optimized LF780 and the LF1152 package have 16 transceivers and no CMU transceiver. Devices in the performance
optimized FF1152 package have 16 transceivers and 8 CMU transceivers.
(7) Devices in the F1152 package have 16 transceivers and eight CMU transceivers. Devices in the performance optimized FF1517 package have
24 transceivers and 12 CMU transceivers.
Table 3–4. HardCopy IV E ASIC Features (Part 1 of 2)
Total Dedicated
ASIC
RAM Bits
18 x 18-Bit
Stratix IV E FPGA Equivalent M9K M144K (not including Multipliers
HardCopy IV E ASIC
Prototype
Gates (1) Blocks Blocks MLABs) (2)
(FIR Mode)
PLLs
HC4E25
EP4SE230
9.2 M
864
22
10,944 Kb
1288
4
EP4SE360
9.4 M
864
32
12,384 Kb
1040
4
© January 2010 Altera Corporation
HardCopy IV Device Handbook, Volume 2