HC4GX15 Datasheet, PDF (71/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 7: External Memory Interfaces in HardCopy IV Devices
7–5
Figure 7–3 shows the memory interface data path that uses all the HardCopy IV I/O
element (IOE) features.
Figure 7–3. External Memory Interface Data Path Overview (Note 1), (2), (3)
HardCopy IV ASIC
Memory
DLL
DQS Logic
Block
DQS (Read)
FIFO
Half-Rate
Resynchronization Clock
4n
2n
2n
Half Data Rate
Input Registers
Alignment &
Synchronization
Registers
DDR Input
Registers
4n
2n
Half Data Rate
Output Registers
Resynchronization Clock
2n
Alignment
Registers
DDR Output
Registers
n
DQ (Read)
n
DQ (Write)
Clock Management & Reset
DQ Write Clock
Half-Rate Clock
Alignment Clock
DQS Write Clock
4
2
Half Data Rate
Output Registers
2
Alignment
Registers
DDR Output
Registers
DQS (Write)
Notes to Figure 7–3:
(1) You can bypass each register block.
(2) The blocks for each memory interface may differ slightly.
(3) These signals may be bidirectional or unidirectional, depending on the memory standard. When bidirectional, the signal is active during both read
and write operations.
© January 2010 Altera Corporation
HardCopy IV Device Handbook, Volume 1