HC4GX15 Datasheet, PDF (437/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: HardCopy IV GX Transceiver Architecture
Functional Modes
1–173
You can configure the word aligner to flip the alignment pattern bits programmed in
the MegaWizard and compare them with the incoming data for alignment. This
feature offers flexibility to the SONET backplane system for either a MSBit-to-LSBit or
LSBit-to-MSBit data transfer. Table 1–48 lists word alignment patterns that you must
program in the ALTGX MegaWizard Plug-In Manager based on the bit-transmission
order and the word aligner bit-flip option.
Table 1–48. Word Aligner Settings
Serial Bit Transmission Order
MSBit-to-LSBit
MSBit-to-LSBit
LSBit-to-MSBit
Word Alignment Bit Flip
On
Off
Off
Word Alignment Pattern
1111011000101000 (16'hF628)
0001010001101111 (16'h146F)
0010100011110110 (16'h28F6)
The behavior of the SONET/SDH word aligner control and status signals, along with
an operational timing diagram, are explained in “Word Aligner in Single-Width Mode
with 8-Bit PMA-PCS Interface Modes” on page 1–74.
OC-48 and OC-96 Byte Serializer and Deserializer
The OC-48 and OC-96 transceiver datapath includes the byte serializer and
deserializer to allow the PLD interface to run at a lower speed. The OC-12
configuration does not use the byte serializer and deserializer blocks.
The byte serializer and deserializer blocks are explained in “Byte Serializer” on
page 1–38 and “Byte Deserializer” on page 1–108, respectively.
The OC-48 byte serializer converts 16-bit data words from the core fabric and
translates the 16-bit data words into two 8-bit data bytes at twice the rate. The OC-48
byte deserializer takes in two consecutive 8-bit data bytes and translates them into a
16-bit data word to the core fabric at half the rate.
The OC-96 byte serializer converts 32-bit data words from the core fabric and
translates them into two 16-bit data words at twice the rate. The OC-96 byte
deserializer takes in two consecutive 16-bit data words and translates them into a
32-bit data word to the core fabric at half the rate.
OC-48 Byte Ordering
Because of byte deserialization, the MSByte of a word might appear at the
rx_dataout port along with the LSByte of the next word.
In an OC-48 configuration, the byte ordering block is built into the datapath and can
be leveraged to perform byte ordering. Byte ordering in an OC-48 configuration is
automatic, as explained in “Word-Alignment-Based Byte Ordering” on page 1–113.
In automatic mode, the byte ordering block is triggered by the rising edge of the
rx_syncstatus signal. As soon as the byte ordering block sees the rising edge of the
rx_syncstatus signal, it compares the LSByte coming out of the byte deserializer
with the A2 byte of the A1A2 alignment pattern. If the LSByte coming out of the byte
deserializer does not match the A2 byte set in the ALTGX MegaWizard Plug-In
Manager, the byte ordering block inserts a PAD character, as seen in Figure 1–143.
Insertion of this PAD character enables the byte ordering block to restore the correct
byte order.
© June 2009 Altera Corporation
HardCopy IV Device Handbook Volume 3