HC4GX15 Datasheet, PDF (23/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: HardCopy IV Device Family Overview
1–13
Architectural Features
Packed with features such as dynamic on-chip termination, trace mismatch
compensation, read and write leveling, half-rate registers, and 4- to 36-bit DQ group
widths, HardCopy IV I/Os supply the built-in functionality required for rapid and
robust implementation of external memory interfaces. Double data-rate support is
found on all sides of the HardCopy IV device. HardCopy IV devices provide an
efficient architecture to quickly and easily fit wide external memory interfaces
precisely.
A self-calibrating soft IP core (ALTMEMPHY) optimized to take advantage of
HardCopy IV device I/Os along with the Quartus II timing analysis tool (the
TimeQuest Timing Analyzer) provides the total solution for the highest reliable
frequency of operation across process, voltage, and temperature (PVT).
f For more information about external memory interfaces, refer to the External Memory
Interfaces in HardCopy IV Devices chapter in volume 1 of the HardCopy IV Device
Handbook.
High-Speed Differential I/O Interfaces with DPA
HardCopy IV devices contain dedicated circuitry for supporting differential
standards at speeds up to 1.25 Gbps. High-speed differential I/O circuitry supports
the following high-speed I/O interconnect standards and applications:
■ Utopia IV
■ SPI-4.2
■ SFI-4
■ 10 Gigabit Ethernet XSLI
■ Rapid I/O
■ NPSI
HardCopy IV devices support 2×, 4×, 6×, 7×, 8×, and 10× SERDES modes for
high-speed differential I/O interfaces, and 4×, 6×, 7×, 8×, and 10× SERDES modes
when using the dedicated DPA circuitry. DPA minimizes bit errors, simplifies PCB
layout and timing management for high-speed data transfer, and eliminates
channel-to-channel and channel-to-clock skews in high-speed data transmission
systems. The Stratix IV soft CDR function can also be implemented using HCells in
HardCopy IV devices, enabling low-cost 1.25-Gbps clock-embedded serial links.
HardCopy IV devices have the following dedicated circuitry for high-speed
differential I/O support:
■ Differential I/O buffer
■ Transmitter serializer
■ Receiver deserializer
■ Data realignment
■ Dynamic phase aligner (DPA)
■ Soft CDR functionality
© January 2010 Altera Corporation
HardCopy IV Device Handbook, Volume 1