HC4GX15 Datasheet, PDF (240/668 Pages) Altera Corporation – HardCopy IV Device Handbook

4–6
Chapter 4: Matching Stratix IV Power and Configuration Requirements with HardCopy IV Devices
HardCopy IV Power-Up Options
Table 4–1. Configuration Pin Compatibility (Note 1), (2), (3)
Stratix IV
HardCopy IV
Pin Name
Function
Board Connection
MSEL [2..0]
Dedicated
No connect on board
nCONFIG (5)
Dedicated
Required connection
DATA [7..0]
Dual-Purpose
DATA[0] retains both user I/O and optional EPCS access
functions. DATA[7..1] retains user I/O functions only
DCLK
Dedicated
No connect on board, except when EPCS access is required in
user mode
INIT_DONE (6)
Dual-Purpose (Optional) Retains the same I/O functions from the Stratix IV device
CLKUSR
Dual-Purpose (Optional) Retains the same I/O functions from the Stratix IV device
nSTATUS (5)
Dedicated
Required connection
CONF_DONE (5)
Dedicated
Required connection
nCE
Dedicated
Required connection
nCEO
Dedicated
Required connection
PORSEL (5)
Dedicated
Required connection
ASDO
Dedicated
No connect on board, except when EPCS access is required in
user mode
nCSO
Dedicated
No connect on board, except when EPCS access is required in
user mode
nIO_PULLUP
Dedicated
Required connection
CRC_ERROR (4)
Dual-Purpose (Optional) Retains the same I/O functions from the Stratix IV device, but
not CRC_ERROR because no device programming is needed.
DEV_CLRn
Dual-Purpose (Optional) Retains the same I/O functions from Stratix IV
DEV_OE
Dual-Purpose (Optional) Retains the same I/O functions from Stratix IV
Notes to Table 4–1:
(1) For correct operation of the HardCopy IV device, pull the nSTATUS, nCONFIG, and CONF_DONE pins to V_CCPGM. In HardCopy IV devices,
these pins are designed with weak internal resistors pulled up to V_CCPGM. Stratix IV configuration schemes require pull-up resistors on these
I/O pins, so they may already be present on the board. You can remove these external pull-up resistors if doing so does not affect other FPGAs
on the board.
(2) HardCopy IV devices have a maximum V_CCIO voltage of 3.0 V, but the input I/O pin can tolerate a 3.3-V level. This applies to V_CCPGM voltage and
all dedicated and dual-purpose pins.
(3) For HardCopy IV devices, there is weak pull-up on the nSTATUS, CONF_DONE, nCONFIG, and DCLK pins. Therefore, these pins can be left
floating or remain connected to external pull-up resistors. If you use Erasable Programmable Configurable Serial (EPCS) in user mode as a
boot-up RAM or data access for a Nios^® II processor, DCLK, DATA[0], ASDO, and nCSO need to be connected to the EPCS device.
(4) In HardCopy IV devices, CRC_ERROR is hard-wired to logic 0 if the CRC feature is enabled in Stratix IV devices.
(5) The PORSEL pin setting delays the POR sequence similar to the prototyping FPGA.
(6) The INIT_DONE settings option is mask-programmed into the device. You must submit these settings to Altera with the final design prior to
mapping to a HardCopy IV device. Using the INIT_DONE option and other dual-purpose pins (for example, the DEV_CLRn device-wide reset
and DEV_OE device-wide output enable) are available in the Fitter Device Options section of the Quartus II report file.
f For more information about PORSEL settings for the FPGA, refer to the Configuration
Handbook.
HardCopy IV Device Handbook, Volume 2
© June 2009 Altera Corporation