HC4GX15 Datasheet, PDF (271/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: HardCopy IV GX Transceiver Architecture
1–7
Transceiver Port List
■ Central control unit (CCU) that implements XAUI state machine for
XGMII-to-PCS code group conversion, XAUI deskew state machine, shared
control signal generation block, PCI Express (PIPE) rateswitch controller block,
and reset control logic
■ The shared control signal generation block provides control signals to the
transceiver channels in bonded functional modes such as XAUI, PIPE, and
Basic ×4.
■ The PIPE rateswitch controller block controls the rateswitch circuit in the CMU0
channel, in ×4 configurations. In PIPE ×8 configuration, the PIPE rateswitch
controller block of the CCU in the master transceiver block is active. For more
information about rateswitch in PIPE, refer to “PCI Express (PIPE) Gen2
(5 Gbps) Support” on page 1–137.
Figure 1–6 shows a block diagram of the transceiver block architecture.
Figure 1–6. Top-Level View of a Transceiver Block
Transceiver Block
Transceiver Channel 3
Transceiver Block
GXBL1
Channel 3
Channel 2
Channel 1
Channel 0
Transceiver Block
GXBL0
Channel 3
Channel 2
Channel 1
Channel 0
Transceiver Block
GXBR1
Channel 3
Channel 2
Channel 1
Channel 0
Transceiver Block
GXBR0
Channel 3
Channel 2
Channel 1
Channel 0
Transceiver Channel 2
Central
Control
Unit (CCU)
CMU1 Channel
CMU0 Channel
Transceiver Channel 1
Transceiver Channel 0
1 For architecture information about CMU channels and transceiver channels, refer to
“CMU Channels” on page 1–22 and “Transceiver Channel Architecture” on
page 1–34.
Transceiver Port List
Instantiate the HardCopy IV GX transceivers using the ALTGX megafunction
instance in the Quartus^® II MegaWizard^™ Plug-In Manager. The ALTGX megafunction
instance allows you to configure transceivers for your intended protocol and select
optional control and status ports to and from the instantiated transceiver channels.
© June 2009 Altera Corporation
HardCopy IV Device Handbook Volume 3