HC4GX15 Datasheet, PDF (374/668 Pages) Altera Corporation – HardCopy IV Device Handbook

1–110
Chapter 1: HardCopy IV GX Transceiver Architecture
Receiver Channel Datapath
Figure 1–94 shows the byte deserializer in double-width mode.
Figure 1–94. Byte Deserializer in Double-Width Mode
dataout[15:0]
or
D1D2 D3D4 D5D6 D7D8
dataout[19:0]
Byte
Deserializer
D3D4
D1D2
D7D8
D5D6
dataout[31:0]
or
dataout[39:0]
/2
Receiver PCS Clock
Byte Ordering Block
In single-width modes with the 16 bit or 20 bit core fabric-transceiver interface, the
byte deserializer receives one data byte (8 or 10 bit) and deserializes it into two data
bytes (16 or 20 bit). Depending on when the receiver PCS logic comes out of reset, the
byte ordering at the output of the byte deserializer may or may not match the original
byte ordering of the transmitted data. The byte misalignment resulting from byte
deserialization is unpredictable because it depends on which byte is being received by
the byte deserializer when it comes out of reset. Figure 1–95 shows a scenario in
which the MSByte and LSByte of the two-byte transmitter data appears straddled
across two word boundaries after getting byte deserialized at the receiver.
Figure 1–95. MSByte and LSByte of the Two-Bit Transmitter Data Straddled Across Two Word Boundaries
Transmitter
Receiver
tx_datain[15:8]
(MSByte)
D2
D4
D6
tx_datain[7:0]
(LSByte)
D1
D3
D5
Byte
Serializer
xx D1 D2 D3 D4 D5 D6 xx
Byte
Deserializer
D1
D3
D5
xx
rx_dataout[15:8]
(MSByte)
xx
rx_dataout[7:0]
D2
D4
D6
(LSByte)
In double-width modes with the 32 bit or 40 bit core fabric-transceiver interface, the
byte deserializer receives two data bytes (16 or 20 bit) and deserializes it into four data
bytes (32 or 40 bit). Figure 1–96 shows a scenario in which the two MSBytes and
LSBytes of the four-byte transmitter data appears straddled across two word
boundaries after getting byte deserialized at the receiver.
HardCopy IV Device Handbook Volume 3
© June 2009 Altera Corporation