HC4GX15 Datasheet, PDF (653/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: DC and Switching Characteristics of HardCopy IV Devices
1–23
Switching Characteristics
Table 1–24. HardCopy IV GX Transceiver Block Jitter Specification (Note 1) and (2) (Part 6 of 6)
Symbol/Description
Conditions
Min Typ
Max Unit
Jitter Frequency = 20KHz
Data Rate = 1.485Gbps (HD)
>1
UI
Pattern = 75% Color Bar
Jitter Frequency = 100KHz
Sinusoidal jitter tolerance (peak-to-peak) Data Rate = 1.485Gbps (HD)
> 0.2
UI
Pattern = 75% Color Bar
Jitter Frequency = 148.5MHz
Data Rate = 1.485Gbps (HD)
> 0.2
UI
Pattern = 75% Color Bar
Notes to Table 1–24:
(1) Dedicated refclk pins were used to drive the input reference clocks.
(2) Jitter numbers specified are valid for the stated conditions only.
(3) The jitter numbers for SONET/SDH are compliant to the GR-253-CORE Issue 3 Specification.
(4) The jitter numbers for Fibre Channel are compliant to the FC-PI-4 Specification revision 6.1.0.
(5) The jitter number for XAUI are compliant to the IEEE802.3ae-2002 Specification.
(6) The jitter numbers for PCI Express are compliant to the PCIe Base Specification 2.0.
(7) The jitter numbers for Serial RapidIO are compliant to the RapidIO Specification 1.3.
(8) The jitter numbers for GIGE are compliant to the IEEE802.3-2002 Specification.
(9) The jitter numbers for HiGig are compliant to the IEEE802.3ae-2002 Specification.
(10) The jitter numbers for (OIF) CEI are compliant to the OIF-CEI-02.0 Specification.
(11) The HD-SDI and 3G-SDI jitter numbers are compliant to the SMPTE292M and SMPTE424M Specifications.
(12) The fibre channel transmitter jitter generation numbers are compliant to the specification at δ_T interoperability point.
(13) The fibre channel receiver jitter tolerance numbers are compliant to the specification at δ_R interoperability point.
Core Performance Specifications
This section describes the clock tree, PLL, DSP, TriMatrix, and configuration and JTAG
specifications.
Clock Tree Specifications
Table 1–25 lists clock tree performance specifications for the logic array, DSP blocks,
and TriMatrix memory blocks for HardCopy IV devices.
Table 1–25. HardCopy IV Clock Tree Performance—Preliminary (Note 1)
Device
Commercial Grade (MHz)
Unit
HC4E25
600
MHz
HC4E35
600
MHz
Note to Table 1–25:
(1) Pending silicon characterization.
PLL Specifications
Table 1–26 describes the HardCopy IV PLL specifications when operating in both the
commercial junction temperature range (0° to 85°C) and the industrial junction
temperature range (–40° to 100°C). For a PLL block diagram, refer to the “PLL
Specifications” row in Table 1–39 on page 1–32.
© June 2009 Altera Corporation
HardCopy IV Device Handbook Volume 4