HC4GX15 Datasheet, PDF (98/668 Pages) Altera Corporation – HardCopy IV Device Handbook

7–32
Chapter 7: External Memory Interfaces in HardCopy IV Devices
HardCopy IV External Memory Interface Features
Phase Offset Control
Each DLL has two phase-offset modules and can provide two separate DQS delay
settings with independent offset, one for the top and bottom I/O banks and one for
the left and right I/O banks, so you can fine-tune the DQS phase shift settings
between two different sides of the device. Even though you have an independent
phase offset control, the frequency of the interface using the same DLL must be the
same. You should use the phase offset control module for making small shifts to the
input signal and use the DQS phase-shift circuitry for larger signal shifts. For
example, if the DLL only offers a multiple of a 30° phase shift, but your interface
requires a 67.5° phase shift on the DQS signal, you can use two delay chains in the
DQS logic blocks to give you a 60° phase shift and use the phase offset control feature
to implement the extra 7.5° phase shift.
You can use either a static phase offset or a dynamic phase offset to implement the
additional phase shift. The available additional phase shift is implemented in
2’s-complement in Gray-code between settings –64 to +63 for frequency modes 0, 1, 2,
and 3, and between settings –32 to +31 for frequency modes 4, 5, and 6. The DQS
phase shift is the sum of the DLL delay settings and the user selected phase offset
settings, which reaches a maximum at setting 64 for mode frequency modes 0, 1, 2 and
3, and a maximum at setting 32 for frequency modes 4, 5, and 6. The actual physical
offset setting range is 64 or 32 subtracted by the DQS delay settings from the DLL.
You must monitor the DQS delay settings to determine how many offsets you can add
and subtract in the system.
1 The DQS delay settings output by the DLL are also Gray-coded.
For example, if the DLL determines that a DQS delay setting of 28 is required to
achieve a 30° phase shift in DLL frequency mode 1, you can subtract up to 28 phase
offset settings and add up to 35 phase offset settings to achieve the optimal delay that
you need. However, if the same DQS delay setting of 28 is required to achieve a 30°
phase shift in DLL frequency mode 4, you can still subtract up to 28 phase offset
settings, but you can only add up to 3 phase offset settings before the DQS delay
settings reach their maximum settings. This is because DLL frequency mode 4 only
uses 5-bit DLL delay settings.
If you use the static phase offset, specify the phase-offset amount in the
ALTMEMPHY megafunction as a positive number for addition or a negative number
for subtraction. You can also have a dynamic phase offset that is always added to,
subtracted from, or both added to and subtracted from the DLL phase shift. When
you always add or subtract, you can dynamically input the phase offset amount into
the dll_offset[5..0] port. When you want to both add and subtract dynamically,
you control the addnsub signal in addition to the dll_offset[5..0] signals.
HardCopy IV Device Handbook, Volume 1
© January 2010 Altera Corporation