HC4GX15 Datasheet, PDF (365/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: HardCopy IV GX Transceiver Architecture
Receiver Channel Datapath
1–101
Figure 1–81 shows the rate match FIFO full condition in Basic single-width mode. The
rate match FIFO becomes full after receiving data byte D4.
Figure 1–81. Rate Match FIFO Full Condition in Basic Single-Width Mode
datain
D1
D2
D3
D4
D5
D6
D7
D8
dataout
D1
D2
D3
D4
D6
D7
D8
xx
xx
xx
rx_rmfifofull
The rate match FIFO automatically inserts /K30.7/ (9'h1FE) after the data byte that
causes the FIFO to go empty and asserts the rx_fifoempty flag synchronous to the
inserted /K30.7/ (9'h1FE).
Figure 1–82 shows the rate match FIFO empty condition in Basic single-width mode.
The rate match FIFO becomes empty after reading out data byte D3.
Figure 1–82. Rate Match FIFO Empty Condition in Basic Single-Width Mode
datain
D1
D2
D3
D4
D5
D6
dataout
D1
D2
D3
/K30.7/
D4
D5
rx_rmfifoempty
Rate Match FIFO in Basic Double-Width Mode
In Basic double-width mode, the rate match FIFO is capable of compensating up to
±300 PPM (total 600 PPM total) difference between the upstream transmitter and the
local receiver reference clock.
1 To enable the rate match FIFO in Basic double-width mode, the transceiver channel
must have both the transmitter and the receiver channel instantiated. You must select
the Receiver and Transmitter option in the What is the operation mode? field in the
ALTGX MegaWizard Plug-In Manager. You must also enable the 8B/10B
encoder/decoder in Basic double-width mode with rate match FIFO enabled.
Depending on your proprietary protocol implementation, you can select two 20-bit
rate match patterns in the ALTGX MegaWizard Plug-In Manager under the What is
the rate match pattern1 and What is the rate match pattern2 fields. Each of the two
programmed 20-bit rate match patterns consists of a 10-bit skip pattern and a 10-bit
control pattern. You must choose 10-bit code groups that have a neutral disparity as
the skip patterns. The rate match FIFO operation begins after the word aligner
synchronization status rx_syncstatus goes high. When the rate matcher receives
either of the two 10-bit control patterns followed by the respective 10-bit skip pattern,
it inserts or deletes a pair of 10-bit skip patterns as necessary to avoid the rate match
FIFO from overflowing or under-running.
© June 2009 Altera Corporation
HardCopy IV Device Handbook Volume 3