HC4GX15 Datasheet, PDF (214/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Table 3–7. HardCopy IV GX ASIC and Stratix IV GX FPGA I/O Bank and Pin Count Mapping (Part 2 of 2) (1)
780-Pin FineLine BGA (2) 780-Pin FineLine BGA (2) 780-Pin FineLine BGA (2) 1152-Pin FineLine BGA (3)
1152-Pin FineLine BGA (3)
1517-Pin FineLine BGA (4)
HC4GX15
EP4SGX70
EP4SGX110
EP4SGX180
EP4SGX230
HC4GX15
EP4SGX290
EP4SGX360
HC4GX25L
EP4SGX290
EP4SGX360
HC4GX25L
(8)
EP4SGX110
HC4GX25L
HC4GX25F
HC4GX35F
EP4SGX180
EP4SGX230
EP4SGX290
EP4SGX360
EP4SGX530
(6)
HC4GX35F
EP4SGX180
EP4SGX230
EP4SGX290
EP4SGX360
EP4SGX530
(7)
7A
40
40
40
40
40
40
40
40
40
40
40
40
7B
—
—
—
—
—
—
—
—
24
24
24
24
7C
24
24
24
32
32
32
24
24
32
32
32
32
8A
40
40
40
40
40
40
40
40
40
40
40
40
8B
—
—
—
—
—
—
—
—
24
24
24
24
8C
24
24
24
32
32
32
24
24
32
32
32
32
Tota 372
372
257
289
289
289
372
372
564
564
l I/O
744
744
Notes to Table 3–7:
(1) User I/O pin counts are preliminary.
(2) All I/O pin counts include four dedicated clock inputs (CLK1p, CLK1n, CLK3p, CLK3n) that can be used for data inputs. The EP4SGX290 and EP4SGX360 mappings include only one dedicated clock
input (CLK1p) that can be used as data input.
(3) All I/O pin counts include four dedicated clock inputs (CLK1p, CLK1n, CLK10p, and CLK10n) that can be used as data inputs.
(4) All I/O pin counts include eight dedicated clock inputs (CLK1p, CLK1n, CLK3p, CLK3n, CLK8p, CLK8n, CLK10p, and CLK10n) that can be used as data inputs.
(5) The EP4SGX290 and EP4SGX360 FPGAs are offered in the H780 package.
(6) The EP4SGX530 FPGA is offered in the H1152 package.
(7) The EP4SGX530 FPGA is offered in the H1517 package.
(8) The HC4GX25L has 564 I/Os, but only 372 I/Os can be mapped if the FPGA EP4SGX110 is selected.
Table 3–8 and Table 3–9 summarize the number of I/O pins available in each I/O bank for all companion pairs of Stratix IV E
and HardCopy IV E devices for socket replacement and non-socket replacement flows, respectively.