HC4GX15 Datasheet, PDF (664/668 Pages) Altera Corporation – HardCopy IV Device Handbook

1–34
Chapter 1: DC and Switching Characteristics of HardCopy IV Devices
Glossary
Table 1–39. Glossary Table (Part 3 of 4)
Letter
Subject
Definitions
SW (sampling
window)
The period of time during which the data must be valid in order to capture it correctly. The
setup and hold times determine the ideal strobe position within the sampling window, as
shown in the following figure:
Bit Time
0.5 x TCCS
RSKM
Sampling Window
(SW)
RSKM
0.5 x TCCS
Timing Diagram
The JEDEC standard for SSTl and HSTL I/O defines both the AC and DC input signal values.
The AC values indicate the voltage levels at which the receiver must meet its timing
specifications. The DC values indicate the voltage levels at which the final logic state of the
receiver is unambiguously defined. Once the receiver input has crossed the AC value, the
receiver changes to the new logic state.
The new logic state is then maintained as long as the input stays beyond the AC threshold.
S
This approach is intended to provide predictable receiver timing in the presence of input
waveform ringing as, shown in the following figure:
Single-ended
voltage
referenced I/O
standard
Single-Ended Voltage Referenced I/O Standard
VOH
V_REF
V_CCIO
VIH (AC )
VIH(DC)
VIL (D C)
VIL (AC )
VOL
V_SS
tC
High-speed receiver/transmitter input and output clock period.
TCCS (channel-
to-channel-skew)
The timing difference between the fastest and slowest output edges, including t_CO variation
and clock skew, across channels driven by the same PLL. The clock is included in the TCCS
measurement (refer to the Timing Diagram figure under S in this table).
HIGH-SPEED I/O Block: Duty cycle on high-speed transmitter output clock.
t_DUTY
T
Timing Unit Interval (TUI)
The timing budget allowed for skew, propagation delays, and data sampling window. (TUI =
1/(Receiver Input Clock Frequency Multiplication Factor) = tC/w)
t FA L L
Signal high-to-low transition time (80-20%)
t I N C CJ
Cycle-to-cycle jitter tolerance on PLL clock input
t O U T P J_ I O
Period jitter on general purpose I/O driven by a PLL
t O U T P J_ D C
Period jitter on dedicated clock output driven by a PLL
tRISE
Signal low-to-high transition time (20-80%)
U
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HardCopy IV Device Handbook Volume 4
© June 2009 Altera Corporation