HC4GX15 Datasheet, PDF (37/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 4: TriMatrix Embedded Memory Blocks in HardCopy IV Devices
4–3
Memory Resources and Features
Table 4–2. HardCopy IV Embedded Memory Features (Part 2 of 2)
Feature
MLABs
M9K Blocks
M144K Blocks
Configurations (depth × width)
64 × 8
8K × 1
16K × 8
64 × 9
4K × 2
16K × 9
64 × 10
2K × 4
8K × 16
32 × 16
1K × 8
8K × 18
32 × 18
1K × 9
4K × 32
32 × 20
512 × 16
4K × 36
512 × 18
2K × 64
256 × 32
2K × 72
256 × 36
Parity bits
v
v
v
Byte enable
v
v
v
Packed mode
—
v
v
Address clock enable
v
v
v
Single-port memory
v
v
v
Simple dual-port memory
v
v
v
True dual-port memory
—
v
v
Embedded shift register
v
v
v
ROM
v
v
v
FIFO buffer
v
v
v
Simple dual-port mixed width support
—
v
v
True dual-port mixed width support
—
v
v
Memory initialization file (.mif)
Not supported, except in Not supported, except in Not supported, except in
ROM mode
ROM mode
ROM mode
Mixed-clock mode
v
v
v
Power-up condition
Outputs cleared if
Outputs cleared
registered, otherwise reads
memory contents (1)
Outputs cleared
Register clears
Outputs cleared
Outputs cleared
Outputs cleared
Write and Read operation triggering
Write: Falling clock edges Write and Read: Rising Write and Read: Rising
Read: Rising clock edges clock edges
clock edges
Same-port read-during-write
Outputs set to old data or Outputs set to old or new Outputs set to old or new
don't care
data
data
Mixed-port read-during-write
Outputs set to old data or Outputs set to old data Outputs set to old data
don't care
ECC Support
Soft IP support using the
Quartus II software
Soft IP support using the
Quartus II software
Built-in support in
×64-wide SDP mode or
soft IP support using the
Quartus II software
Note to Table 4–2:
(1) The memory contents for the MLAB in RAM mode are initialized to zero on power-up.
© January 2010 Altera Corporation
HardCopy IV Device Handbook, Volume 1