HC4GX15 Datasheet, PDF (296/668 Pages) Altera Corporation – HardCopy IV Device Handbook

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Chapter 1: HardCopy IV GX Transceiver Architecture
Auxiliary Transmit (ATX) PLL Block
Auxiliary Transmit (ATX) PLL Block
The HardCopy IV GX transceiver contains the ATX PLL block that you can use to
generate high-speed clocks for the transmitter channels on the same side of the
device. The following data rates are supported by the ATX PLLs:
■ 4.8 Gbps to 5.4 Gbps and 6.0 Gbps to 6.5 Gbps
Using the dividers available in the ATX PLLs:
■ 2.4 Gbps to 2.7 Gbps and 3.0 Gbps to 3.25 Gbps
■ 1.2 Gbps to 1.35 Gbps and 1.5 Gbps to 1.625 Gbps
Figure 1–14, Figure 1–15, and Figure 1–16 show the location of the ATX PLL blocks in
two, three, and four transceiver block device families.
Figure 1–14. Location of ATX PLL Block in a Two-Transceiver Block Device
GXBR1
ATX PLL R0
GXBR0
Figure 1–15. Location of ATX PLL Blocks in a Four-Transceiver Block Device (Two on Each Side)
GXBL1
GXBR1
ATX PLL L0
ATX PLL R0
GXBL0
GXBR0
Figure 1–16. Location of ATX PLL Blocks in a Six-Transceiver Block Device
GXBL2
ATX PLL L1
GXBL1
ATX PLL L0
GXBL0
GXBR2
ATX PLL R1
GXBR1
ATX PLL R0
GXBR0
HardCopy IV Device Handbook Volume 3
© June 2009 Altera Corporation