HC4GX15 Datasheet, PDF (96/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Figure 7–18. Simplified Diagram of the DQS Phase Shift Circuitry (Note 1)
addnsub_a
Phase offset settings
from the core array
Input Reference
Clock (2)
DLL
upndn
Phase
Comparator clock enable
Up/Down
Counter
6
Phase
Offset
Control 6
addnsub_b
Phase offset settings
from the core array
6
Phase
Offset
Control 6
Phase offset
settings to DQS pins
on top or bottom edge (3)
Phase offset
settings to DQS pin
on left or right edge (3)
Delay Chains
6
6
DQS Delay
Settings (4)
6
Note to Figure 7–18:
(1) All features of the DQS phase-shift circuitry are accessible from the ALTMEMPHY MegaWizard^™ Plug-In Manager in the Quartus II software.
(2) For exact PLL and input clock pin information, the input reference clock for the DQS phase-shift circuitry can come from a PLL output clock or an
input clock pin. Refer to Table 7–9 and Table 7–13.
(3) Phase offset settings can go only to the DQS logic blocks.
(4) DQS delay settings can go to the core array, the DQS logic block, and the leveling circuitry.
The DLL can be reset from either the core array or a user I/O pin. Each time the DLL is reset, you must wait for 1,280 clock
cycles before you can capture the data properly.
Depending on the DLL frequency mode, the DLL can shift the incoming DQS signals by 0°, 22.5°, 30°, 36°, 45°, 60°, 67.5°, 72°,
90°, 108°, 120°, 135°, 144°, or 180°. The shifted DQS signal is then used as the clock for the DQ IOE input registers.