HC4GX15 Datasheet, PDF (274/668 Pages) Altera Corporation – HardCopy IV Device Handbook

1–10
Chapter 1: HardCopy IV GX Transceiver Architecture
Transceiver Port List
Table 1–2. HardCopy IV GX ALTGX Megafunction Ports (Part 3 of 14)
Port Name
rx_syncstatus
rx_bitslip
rx_ala2size
rx_rlv
Input/Output
Description
Output
Word alignment synchronization status
indicator. For the word aligner in automatic
synchronization state machine mode, this
signal is driven high if the conditions required
to remain in synchronization are met. It is
driven low if the conditions required to lose
synchronization are met.
For the word aligner in manual alignment mode,
the behavior of this signal depends on whether
the transceiver is configured in single-width or
double-width mode.
For more information, refer to “Word Aligner in
Single-Width Mode” on page 1–74 and “Word
Aligner in Double-Width Mode” on page 1–80.
This signal is not available for the word aligner
in bit-slip mode.
The width of this signal depends on the
following channel width:
Channel Width rx_syncstatus
8/10
1
16/20
2
32/40
4
Input
Bit-slip control for the word aligner configured
in bit-slip mode. At every rising edge of this
signal, word aligner slips one bit into the
received data stream, effectively shifting the
word boundary by 1 bit.
Asynchronous signal. The minimum
pulse-width is two recovered clock cycles.
Input
Available only in SONET OC-12 and OC-48
modes to select between one of the following
two word alignment options:
■ 0 -16-bit A1A2
■ 1 - 32-bit A1A1A2A2
Output
Run-length violation indicator. A high pulse is
driven when the number of consecutive 1s or
0’s in the received data stream exceeds the
programmed run length violation threshold.
Asynchronous signal. Driven for a minimum of
two recovered clock cycles in configurations
without byte serializer and a minimum of three
recovered clock cycles in configurations with
byte serializer.
Scope
Channel
Channel
Channel
Channel
HardCopy IV Device Handbook Volume 3
© June 2009 Altera Corporation