HC4GX15 Datasheet, PDF (20/668 Pages) Altera Corporation – HardCopy IV Device Handbook

1–10
Chapter 1: HardCopy IV Device Family Overview
Architectural Features
■ Memory Initialization Files (.mif) for embedded memories used as RAM are not
supported. The .mifs for memories used as ROM are supported, because the data
are mask-programmed into the memory cells.
■ Stratix IV LAB, MLAB, and DSP functions are implemented with HCells in
HardCopy IV devices instead of dedicated blocks. However, they remain
functionally and electrically equivalent between the FPGAs and the HardCopy
ASICs.
■ Stratix IV programmable power technology is not supported in HardCopy IV
devices. However, the HardCopy IV architecture offers performance similar to
Stratix IV devices with significantly lower power consumption.
■ There are eight on-chip termination (OCT) calibration blocks in HardCopy IV
devices instead of up to 10 OCT calibration blocks in Stratix IV devices.
Architectural Features
This section describes the architectural features of HardCopy IV ASICs.
Logic Array Block and Adaptive Logic Module Function Support
HardCopy IV devices fully support the Stratix IV LAB and ALM functions. The basic
building blocks of Stratix IV LABs are composed of ALMs that you can configure to
implement logic, arithmetic, and register functions. Each LAB consists of 10 ALMs,
carry chains, shared arithmetic chains, LAB control signals, local interconnect, and
register chain connection lines.
In HardCopy IV devices, the basic building blocks of the core array are HCells, which
are a collection of logic transistors connected together to provide the same
functionality as the Stratix IV LABs and ALMs. The Quartus II software maps these
LAB and ALM functions to HCell macros, which define how the HCells are connected
together in the HardCopy IV core array. Only HCells required to implement the
customer design are used, and unused HCells are powered down. This allows
efficient use of the core fabric and offers significant static power savings.
The Stratix IV LAB derivative, called MLAB, is also supported in HardCopy IV
devices. MLAB adds static random access memory (SRAM) capability to the LAB and
can provide a maximum of 640 bits of simple dual-port SRAM. Like the LAB
functions, the Quartus II software maps MLAB functions to HCell macros in
HardCopy IV devices to provide the same Stratix IV functionality.
f For more information about LABs and ALMs, refer to the Logic Array Block and
Adaptive Logic Module Implementation in HardCopy IV Devices chapter in volume 1 of
the HardCopy IV Device Handbook.
f For more information about MLAB modes, features, and design considerations, refer
to the TriMatrix Embedded Memory Blocks in HardCopy IV Devices chapter in volume 1
of the HardCopy IV Device Handbook.
HardCopy IV Device Handbook, Volume 1
© January 2010 Altera Corporation