HC4GX15 Datasheet, PDF (45/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 5: Clock Networks and PLLs in HardCopy IV Devices
5–5
PLLs in HardCopy IV Devices
Table 5–3. HardCopy IV GX Device PLL Availability (Part 2 of 2)
HardCopy IV GX
Device
Stratix IV
Prototype Device
L1 L2 L3 L4 T1 T2 B1 B2 R1 R2 R3 R4
EP4SGX230KF40 (F1517) — v — — v v v v — v — —
HC4GX35LF1517N ^{EP4SGX360KF40 (F1517) — v}
EP4SGX530KH40 (H1517) — _v
——v vv v
——v vv v
—v
—v
——
——
EP4SGX180KF40 (F1517) — _{v v} — _{v v v v} — _{v v} —
EP4SGX230KF40 (F1517) — _{v v} — _{v v v v} — _{v v} —
HC4GX35FF1517N EP4SGX290KF40 (F1517) — v v — v v v v — v v —
EP4SGX360KF40 (F1517) — _{v v} — _{v v v v} — _{v v} —
EP4SGX530KH40 (H1517) — _{v v} — _{v v v v} — _{v v} —
The PLL functionality in HardCopy IV devices remains the same in Stratix IV PLLs.
Therefore, HardCopy IV PLLs also support features such as PLL reconfiguration,
where you can dynamically configure the PLL in user mode.
All HardCopy IV PLLs have the same core analog structure with only minor
differences in features that are supported. Table 5–4 lists the features of the
top/bottom and left/right PLLs in HardCopy IV devices.
f For more information about Stratix IV PLL features, refer to the Clock Networks and
PLLs in Stratix IV Devices chapter in volume 1 of the Stratix IV Device Handbook.
Table 5–4. HardCopy IV PLL Features (Part 1 of 2)
Feature
C (output) counters
M, N, C counter sizes
Dedicated clock outputs
Clock input pins
External feedback input pin
Spread-spectrum input clock
tracking
PLL cascading
Compensation modes
PLL drives LVDSCLK and LOADEN
VCO output drives DPA clock
Phase shift resolution
Programmable duty cycle
Output counter cascading
HardCopy IV Top/Bottom PLLs
10
1 to 512
6 single-ended or 4 single-ended and 1
differential pair
8 single-ended or 4 differential pin pairs
Single-ended or differential
Yes (1)
Through GCLK and RCLK and dedicated
path between adjacent PLLs
All except LVDS clock network
compensation
No
No
Down to 96.125ps (3)
Yes
Yes
HardCopy IV Left/Right PLLs
7
1 to 512
2 single-ended or 1 differential pair
8 single-ended or 4 differential pin pairs
Single-ended only
Yes (1)
Through GCLK and RCLK and dedicated
path between adjacent PLLs (2)
All except external feedback mode when
using differential I/Os
Yes
Yes
Down to 96.125ps (3)
Yes
Yes
© January 2010 Altera Corporation
HardCopy IV Device Handbook, Volume 1