HC4GX15 Datasheet, PDF (275/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: HardCopy IV GX Transceiver Architecture
Transceiver Port List
Table 1–2. HardCopy IV GX ALTGX Megafunction Ports (Part 4 of 14)
Port Name
rx_invpolarity
rx_revbitorderwa
rx_revbyteorderwa
Input/Output
Description
Input
Generic receiver polarity inversion control.
Useful feature for correcting situations where
the positive and negative signals of the
differential serial link are accidentally swapped
during board layout. When asserted high in
single-width modes, the polarity of every bit of
the 8-bit or 10-bit input data word to the word
aligner gets inverted.
When asserted high in double-width mode, the
polarity of every bit of the 16-bit or 20-bit input
data to the word aligner gets inverted.
Asynchronous signal.
Input
Receiver bit reversal control. This is available
only in Basic single-width and double-width
modes with the word aligner configured in
bit-slip mode. This is a useful feature where the
link transmission order is MSBit to LSBit.
When asserted high in Basic single-width
modes, the 8-bit or 10-bit data D[7:0] or
D[9:0] at the output of the word aligner gets
rewired to D[0:7] or D[0:9], respectively.
When asserted high in Basic double-width
modes, the 16-bit or 20-bit data D[15:0] or
D[19:0] at the output of the word aligner
gets rewired to D[0:15] or D[0:19],
respectively.
Asynchronous signal.
Input
Receiver byte reversal control. This is available
only in Basic double-width mode. This is a
useful feature in situations where the MSByte
and LSByte of the transmitted data are
erroneously swapped.
When asserted high, the MSByte and LSByte of
the 16 and 20 bit data at the output of the word
aligner get swapped.
Asynchronous signal.
1–11
Scope
Channel
Channel
Channel
© June 2009 Altera Corporation
HardCopy IV Device Handbook Volume 3