HC4GX15 Datasheet, PDF (21/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: HardCopy IV Device Family Overview
1–11
Architectural Features
DSP Function Support
HardCopy IV devices fully support the DSP block functions of Stratix IV devices.
Complex systems such as WiMAX, 3GPP WCDMA, CDMA2000, voice over Internet
protocol (VoIP), H.264 video compression, and high-definition television (HDTV)
require high-performance DSP circuits to handle large amounts of data with high
throughput. These system designs typically use DSP to implement finite impulse
response (FIR) filters, complex FIR filters, infinite impulse response (IIR) filters, fast
Fourier transform (FFT) functions, and discrete cosine transform (DCT) functions.
In HardCopy IV devices, these DSP block functions are implemented with HCells.
The Quartus II software maps the Stratix IV DSP functions to HCell macros in
HardCopy IV devices, preserving the same functionality. Implementing DSP
functions using HCells also allows efficient use of the HardCopy IV device core fabric
and offers significant static power savings.
HardCopy IV devices support all Stratix IV DSP configurations (9 × 9, 12 × 12, 18 × 18,
and 36 × 36 multipliers) and block features, such as dynamic sign controls, dynamic
addition and subtraction, dynamic rounding and saturation, and dynamic input shift
registers. All five operational modes of the Stratix IV DSP block are supported:
■ Independent multiplier (9 × 9, 12 × 12, 18 × 18, and 36 × 36)
■ Two-multiplier adder
■ Four-multiplier adder
■ Multiply accumulate
■ Shift mode
f For more information about DSP blocks, refer to the DSP Block Implementation in
HardCopy IV Devices chapter in volume 1 of the HardCopy IV Device Handbook.
TriMatrix Embedded Memory Blocks
TriMatrix embedded memory blocks provide three different sizes of embedded
SRAM to efficiently address the needs of HardCopy IV ASIC designs. TriMatrix
memory includes the following types of blocks:
■ 640-bit MLAB blocks optimized to implement filter delay lines, small FIFO buffers,
and shift registers. MLAB blocks are implemented in HCell macros.
■ 9-Kbit M9K blocks that can be used for general purpose memory applications.
■ 144-Kbit M144K blocks that are ideal for processor code storage, packet, and video
frame buffering.
You can configure each embedded memory block independently to be a single- or
dual-port RAM, ROM, or shift register using the Quartus II MegaWizard^™ Plug-In
Manager. Multiple blocks of the same type can also be stitched together to produce
larger memories with minimal timing penalty. TriMatrix memory provides up to an
equivalent of 20.3 Mbits of dedicated, embedded SRAM.
f For more information about TriMatrix memory blocks, modes, features, and design
considerations, refer to the TriMatrix Embedded Memory Blocks in HardCopy IV Devices
chapter in volume 1 of the HardCopy IV Device Handbook.
© January 2010 Altera Corporation
HardCopy IV Device Handbook, Volume 1