HC4GX15 Datasheet, PDF (395/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: HardCopy IV GX Transceiver Architecture
Functional Modes
Figure 1–107. Transmitter Buffer Electrical Idle State
tx_forcelecidle
tx_dataout
1–131
T1
>20 ns
The PCI Express (PIPE) specification requires the transmitter buffer to be in electrical
idle in certain power states. For more information about the tx_forceelecidle
signal levels required in different PIPE power states, refer to Table 1–31 on
page 1–128.
Receiver Detection
During the detect substate of the link training and status state machine (LTSSM), the
PIPE protocol requires the transmitter channel to perform a receiver detect sequence
to detect if a receiver is present at the far end of each lane. The PIPE specification
requires the receiver detect operation to be performed during the P1 power state.
The PIPE interface block in HardCopy IV GX transceivers provides an input signal
tx_detectrxloopback for the receiver detect operation. When the input signal
tx_detectrxloopback is asserted high in the P1 power state, the PIPE interface
block sends a command signal to the transmitter buffer in that channel to initiate a
receiver detect sequence. In the P1 power state, the transmitter buffer must always be
in the electrical idle state. After receiving this command signal, the receiver detect
circuitry creates a step voltage at the output of the transmitter buffer. If an active
receiver (that complies to the PIPE input impedance requirements) is present at the far
end, the time constant of the step voltage on the trace is higher than when the receiver
is not present. Receiver detect circuitry monitors the time constant of the step signal
seen on the trace to determine if a receiver was detected. The receiver detect circuitry
monitor needs a 125-MHz clock for operation that you must drive on the fixedclk
port.
1 For the receiver detect circuitry to function reliably, the AC-coupling capacitor on the
serial link and the receiver termination values used in your system must be compliant
to the PCI Express (PIPE) Base Specification 2.0.
Receiver detect circuitry communicates the status of the receiver detect operation to
the PIPE interface block. If a far-end receiver is successfully detected, the PIPE
interface block asserts pipephydonestatus for one clock cycle and synchronously
drives the pipestatus[2:0] signal to 3'b011. If a far-end receiver is not detected,
the PIPE interface block asserts pipephydonestatus for one clock cycle and
synchronously drives the pipestatus[2:0] signal to 3'b000.
Figure 1–108 and Figure 1–109 show the receiver detect operation where a receiver
was successfully detected and where a receiver was not detected, respectively.
© June 2009 Altera Corporation
HardCopy IV Device Handbook Volume 3