HC4GX15 Datasheet, PDF (567/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 2: HardCopy IV GX Dynamic Reconfiguration
Description of Transceiver Channel Reconfiguration Modes
2–109
Figure 2–51 depicts a .mif write transaction in CMU PLL Reconfiguration mode.
Figure 2–51. CMU PLL Reconfiguration—.mif Write Transaction
reconfig_mode_sel[2:0]
3’b100
reconfig_clk
write_all
busy
reconfig_address_out[5:0]
Addr0
Addr1
Addr37
Addr0
reconfig_address_en
reconfig_data[15:0] (1)
channel_reconfig_done
1^st 16-bits
Don’t care
2^nd 16-bits
27^th 16-bits
Don’t care
Note to Figure 2–51:
(1) This waveform assumes that the transceiver channel is configured in Receiver and Transmitter configuration. Therefore, the .mif size is 8.
The logical_tx_pll_sel and logical_tx_pll_sel_en Ports
This section describes when to enable the logical_tx_pll_sel and
logical_tx_pll_sel_en ports and how to use them in the following dynamic
reconfiguration modes:
■ Channel and CMU PLL Reconfiguration mode
■ Channel Reconfiguration with TX PLL select mode
■ CMU PLL Reconfiguration mode
These are optional input ports to the ALTGX_RECONFIG instance. The
logical_tx_pll_sel and logical_tx_pll_sel_en ports are enabled by
default when you enable the Channel and TX PLL select/reconfig option.
When you disable the logical_tx_pll_sel and logical_tx_pll_sel_en
ports, the dynamic reconfiguration controller uses the logical reference index of the
CMU PLL stored in the .mif generated (logical tx pll).
When you enable the logical_tx_pll_sel and logical_tx_pll_sel_en
ports, the dynamic reconfiguration controller uses the value at
logical_tx_pll_sel to identify the CMU PLL, only when you set
logical_tx_pll_sel_en to 1'b1.
© June 2009 Altera Corporation
HardCopy IV Device Handbook, Volume 3