HC4GX15 Datasheet, PDF (315/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: HardCopy IV GX Transceiver Architecture
1–51
Transmitter Channel Datapath
Figure 1–38 shows the transmitter bit reversal feature in Basic double-width mode for
a 20-bit wide datapath configuration.
Figure 1–38. Transmitter Bit Reversal Operation in Basic Double-Width Mode
Output from transmitter PCS
Converted data output to the
transmitter serializer
TX bit reversal option enabled
in the ALTGX MegaWizard
D[19]
D[18]
D[17]
D[16]
D[15]
D[14]
D[13]
D[12]
D[11]
D[10]
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
D[0]
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
D[8]
D[9]
D[10]
D[11]
D[12]
D[13]
D[14]
D[15]
D[16]
D[17]
D[18]
D[19]
Serializer
The serializer converts the incoming low-speed parallel signal from the transceiver
PCS to high-speed serial data and sends it to the transmitter buffer. The serializer
supports an 8-bit or 10-bit serialization factor in single-width mode and a 16-bit or
20-bit serialization factor in double-width mode. The serializer block drives the serial
data to the output buffer, as shown in Figure 1–39. The serializer block sends out the
least significant bit of the input data. Figure 1–40 shows the serial bit order of the
serializer block output. In this example, a constant 8'h6A (01101010) value is serialized
and the serial data is transmitted from LSBit to MSBit.
© June 2009 Altera Corporation
HardCopy IV Device Handbook Volume 3