HC4GX15 Datasheet, PDF (400/668 Pages) Altera Corporation – HardCopy IV Device Handbook

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Chapter 1: HardCopy IV GX Transceiver Architecture
Functional Modes
If the HardCopy IV GX receiver CDR is configured in Automatic Lock mode, the
receiver cannot meet the PCI Express (PIPE) specification of acquiring bit and byte
synchronization within 4 μs (Gen1 data rate) or 2 μs (Gen2 data rate) due to the signal
detect and PPM detector time. To meet this specification, each HardCopy IV GX
transceiver has a built-in Fast Recovery circuitry that you can optionally enable.
1 To enable the Fast Recovery circuitry, select the Enable fast recovery mode option in
the ALTGX MegaWizard Plug-In Manager.
If you enable the Fast Recovery mode option, the Fast Recovery circuitry controls the
receiver CDR rx_locktorefclk and rx_locktodata signals to force the receiver
CDR in LTR or LTD mode. It relies on the Electrical Idle Ordered Sets (EIOS), N_FTS
sequences received in the L0 power state, and the signal detect signal from the
receiver input buffer to control the receiver CDR lock mode.
1 The Fast Recovery circuitry is self-operational and does not require control inputs
from you. When enabled, the rx_locktorefclk and rx_locktodata ports are not
available in the ALTGX MegaWizard Plug-In Manager.
Electrical Idle Inference
The PIPE protocol allows inferring the electrical idle condition at the receiver instead
of detecting the electrical idle condition using analog circuitry. Clause 4.2.4.3 in the
PIPE Base Specification 2.0 specifies conditions to infer electrical idle at the receiver in
various substates of the LTSSM state machine.
In all PIPE modes (×1, ×4, and ×8), each receiver channel PCS has an optional
Electrical Idle Inference module designed to implement the electrical idle inference
conditions specified in the PIPE Base Specification 2.0. You can enable the Electrical
Idle Inference module by selecting the Enable electrical idle inference functionality
option in the ALTGX MegaWizard Plug-In manager.
If enabled, this module infers electrical idle depending on the logic level driven on the
rx_elecidleinfersel[2:0] input signal. The Electrical Idle Inference module in
each receiver channel indicates whether the electrical idle condition is inferred or not
on the pipeelecidle signal of that channel. The Electrical Idle Interface module
drives the pipeelecidle signal high if it infers an electrical idle condition;
otherwise, it drives it low.
Table 1–36 shows electrical idle inference conditions specified in the PIPE Base
Specification 2.0 and implemented in the Electrical Idle Inference module to infer
electrical idle in various substates of the LTSSM state machine. For the Electrical Idle
Inference Module to correctly infer an electrical idle condition in each LTSSM
substate, you must drive the rx_elecidleinfersel[2:0] signal appropriately, as
shown in Table 1–36.
Table 1–36. Electrical Idle Inference Conditions (Part 1 of 2)
LTSSM State
Gen1 (2.5 Gbps)
Gen2 (5 Gbps)
rx_elecidleinfersel[2:0]
L0
Recovery.RcvrCfg
Absence of skip ordered set in
128 μs window
Absence of TS1 or TS2
ordered set in 1280 UI interval
Absence of skip ordered set in
128 μs window
Absence of TS1 or TS2
ordered set in 1280 UI interval
3'b100
3'b101
HardCopy IV Device Handbook Volume 3
© June 2009 Altera Corporation