HC4GX15 Datasheet, PDF (100/668 Pages) Altera Corporation – HardCopy IV Device Handbook

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Chapter 7: External Memory Interfaces in HardCopy IV Devices
HardCopy IV External Memory Interface Features
The delay elements in the DQS logic block have the same characteristics as the delay
elements in the DLL. When the DLL does not control the DQS delay chains, you can
input your own Gray-coded 6-bit or 5-bit settings using the
dqs_delayctrlin[5..0] signals available in the ALTMEMPHY megafunction.
These settings control 1, 2, 3, or all 4 delay elements in the DQS delay chains. The
ALTMEMPHY megafunction can also dynamically choose the number of DQS delay
chains required for the system. The amount of delay is equal to the sum of the delay
element’s intrinsic delay and the product of the number of delay steps and the value
of the delay steps.
You can also bypass the DQS delay chain to achieve a 0° phase shift.
f For more information about the ALTMEMPHY megafunction, refer to the External
DDR Memory PHY Interface Megafunction User Guide (ALTMEMPHY).
Update Enable Circuitry
Both the DQS delay settings and the phase-offset settings pass through a register
before entering the DQS delay chains. The registers are controlled by the update
enable circuitry to allow enough time for changes in the DQS delay setting bits to
arrive at all the delay elements. This allows them to be adjusted at the same time. The
update enable circuitry enables the registers to allow enough time for the DQS delay
settings to travel from the DQS phase-shift circuitry or core logic to all the DQS logic
blocks before the next change. It uses the input reference clock or a user clock from the
core to generate the update enable output. The ALTMEMPHY megafunction uses this
circuit by default. Figure 7–20 shows an example waveform of the update enable
circuitry output.
Figure 7–20. DQS Update Enable Waveform
DLL Counter Update
(Every 8 cycles)
DLL Counter Update
(Every 8 cycles)
System Clock
DQS Delay Settings
(Updated every 8 cycles)
6 bit
Update Enable
Circuitry Output
DQS Postamble Circuitry
For external memory interfaces that use a bidirectional read strobe such as DDR3,
DDR2, and DDR SDRAM, the DQS signal is low before going to or coming from a
high-impedance state. The state where DQS is low, just after a high-impedance state,
is called the preamble state; the state where DQS is low, just before it returns to a
high-impedance state, is called the postamble state. There are preamble and
postamble specifications for both read and write operations in DDR3, DDR2, and
DDR SDRAM.
HardCopy IV Device Handbook, Volume 1
© January 2010 Altera Corporation